The transfer of data between various units in a data-processing system is normally effected by a physical connection between an output latch on the transmitting unit and an input latch on the receiving unit This requires that the data be clocked into the input latch as it is received over the physical connection. At relatively low clock frequencies a system-wide clock can be used for this purpose. However, with high clock frequencies, corresponding with high data-transfer rates, clock skew, i.e. the difference in clock phase in different points in the system, presents a problem. Specifically, the clock edges at which the data is clocked into the input latches may not occur at the times the incoming data is received, resulting in errors in data reception.
To overcome this problem various clock-forwarding arrangements have been used, with transmitting units sending their clock signals to the receiving units along with the data. The clock signals arrive at the input latches of the latter units along with the data and the data is therefore clocked into the latches with greatly reduced clock-skew error.
Once received, the data must be moved from the input latch to other components that are to process the data in accordance with the function of the receiving unit. These components operate in synchronism with a local clock and the transfers from the input latch must therefore be effected in such manner as to accommodate the phase differences between the forwarded clock and the local clock. One can use a FIFO buffer for this purpose, the input latch being the input stage of the buffer. The buffer can thus be loaded in accordance with the forwarded clock and unloaded in accordance with the local clock. However to insure proper operation the buffer must be large enough to contain the largest burst of data that will be received by the receiving unit. This results in undue latency in each transfer, since incoming data must pass through the successive stages of the buffer before it is accessible to the receiving unit.
As connection lengths between the transmitting node and the receiving node change in a clock forwarded system, so does the phase relationship between the forwarded clock seen at the receiving node and the local clock at the receiving node. One can account for these phase differences by pre-calculating the expected phase differences and accounting for these differences in the receive logic by modifying when data is first removed from the FIFO. This has the advantage of reducing latency, but each time the connection length is changed, calculations must be made and the operation of the receive logic must be modified (which is typically accomplished via register bits that are written by an external means) in order to account for the change in length. In cases where connections between the transmitting node and the receive node are of great length, process variations within a standard connection length used may result in skews too great to be able to correct. In this instance, larger FIFOs must be again utilized and latencies increase and bandwidths suffer.